# REQUIRES: amdgpu-registered-target
# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir -mtriple=amdgcn-amd-amdhsa --delta-passes=instructions --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --check-prefix=RESULT %s < %t

# Make sure there's no crash with unreachable blocks.

# CHECK-INTERESTINGNESS: S_NOP

# RESULT: bb.0:

# RESULT: %{{[0-9]+}}:vgpr_32 = IMPLICIT_DEF
# RESULT-NEXT: %{{[0-9]+}}:sreg_64 = IMPLICIT_DEF
# RESULT-NEXT: %{{[0-9]+}}:vreg_64 = IMPLICIT_DEF
# RESULT-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
# RESULT-NEXT: S_BRANCH %bb.3

# RESULT: bb.1:
# RESULT-NEXT: S_BRANCH %bb.3

# RESULT: bb.2:
# RESULT-NEXT: S_NOP 0, implicit %{{[0-9]+}}, implicit killed %{{[0-9]+}}, implicit %{{[0-9]+}}

---
name: unreachable_block
tracksRegLiveness: true
body:             |
  bb.0:
    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    S_CBRANCH_SCC1 %bb.1, implicit undef $scc
    S_BRANCH %bb.3

  bb.1:
    %1:sreg_64 = S_MOV_B64 0
    S_BRANCH %bb.3

  bb.2:
    %2:vreg_64 = IMPLICIT_DEF
    S_NOP 0, implicit %0, implicit killed %2, implicit %1
    S_BRANCH %bb.3

  bb.3:

...
